1. Field of the Invention
The present invention relates to a thin-film transistor device, a method of manufacturing the same, a thin-film transistor substrate provided therewith and a display device. More particularly, the invention relates to a thin-film transistor device having two kinds of polycrystalline silicon thin-film transistors of different types of electric conduction on the same substrate, a method of manufacturing the same, a thin-film transistor substrate provided therewith and a display device.
2. Description of the Related Art
Owing to its light weight, small thickness and low power consumption, a liquid crystal display device (LCD) has been used in wide field of applications such as finders of portable data terminals and video cameras and as display units of notebook PCs (personal computers). In order to decrease the cost, there has nowadays been widely used an LCD of the type of integrally forming the peripheral circuits of TFTs surrounding the display region while forming the thin-film transistors (TFTs) for driving the pixels in the display region. Polycrystalline silicon TFTs (p-Si TFTs) are used as the TFTs for driving pixels and as TFTs for the peripheral circuits in the LCD of the type of integrally forming the peripheral circuits.
The p-Si TFTs for driving the pixels must be fabricated in an LDD structure having a low density impurity implantation region (LDD—lightly doped drain region) formed among the channel region, a source region and a drain region to decrease the defective display caused by the leakage of current. The p-Si TFT for the peripheral circuit, on the other hand, is better not provided with the LDD region since provision of the LDD region results in a decrease in the operation speed and, besides, it is little affected by the leakage of current.
However, the n-ch TFT (TFT having n-type of electric conduction) without LDD region exhibits characteristics that are deteriorated due to hot carriers and, generally, exhibits lower reliability than that of the n-ch TFT having the LDD region. Through experiments conducted thus far, the present inventors have discovered that deterioration in the characteristics due to hot carriers can be decreased yet maintaining a sufficient operation speed of the TFTs upon employing a structure of providing the LDD region and covering the whole LDD region with the gate electrode (gate overlapping LDD structure, hereinafter referred to as GOLD structure). Concerning the TFT for driving the pixel, if there is employed a structure further provided with a conventional LDD region that is not covered with the gate electrode (hereinafter referred to as “partial GOLD structure”) in addition to the GOLD structure, then, the off current can be decreased while achieving a high reliability. In the TFT of the GOLD structure, the LDD region as a whole is covered with the gate electrode while in the TFT of the partial GOLD structure, a portion neighboring the channel region in the LDD structure is covered with the gate electrode but other portions are not covered with the gate electrode.
Table 1 shows in comparison the characteristics and reliability of n-ch TFTs depending upon differences in the structure.
TABLE 1TFT1TFT2TFT3TFT4Type of conductionn-typen-typen-typen-typeLDD structurex∘xxGOLD structurexx∘xPartial GOLD structurexxx∘On-current∘∘∘∘∘∘Off-current∘∘∘∘∘∘Hot-carrier deteriorationxx∘∘High-speed circuitxx∘∘∘Pixelxxx∘
In Table 1, TFT1 represents an n-ch TFT of the non-LDD structure and of the non-GOLD structure, TFT2 represents an n-ch TFT of the LDD structure and of the non-GOLD structure, TFT3 represents an n-ch TFT of the GOLD structure and TFT4 represents an n-ch TFT of the partial GOLD structure. As shown in Table 1, the TFT3 of the GOLD structure and the TFT4 of the partial GOLD structure exhibit less deterioration due to hot carriers and higher reliability than those of the TFT1 and TFT2 of the non-GOLD structure. When the TFT3 is compared with the TFT4, the TFT3 is suited for the high-speed circuit (peripheral circuit) on account of its large on-current, but is not suited for driving the pixel due to its large off-current. The TFT4, on the other hand, has a slightly small on-current and a small off-current, and is suited for driving the pixel. The p-ch TFT (TFT having p-type of electric conduction) exhibits characteristics that are not almost deteriorated by hot carriers and needs not have the LDD region.
To lower the consumption of electric power, it is desired that the peripheral circuits are constituted by CMOS circuits. When the CMOS circuits are used, it is important to control the threshold value of the TFTs. In general, the p-Si TFT has a threshold voltage of a negative sign (smaller than 0 V). Therefore, the channel region must be doped with impurities of the p-type such as boron (B) at a low concentration (hereinafter also referred to as “channel doping”). The n-ch TFT and the p-ch TFT exhibit threshold voltages that are shifted in different amounts for the amount of boron with which they are doped. Therefore, to maintain a sufficient difference in the threshold value between the n-ch TFT and the p-ch TFT, the boron concentration in the channel region of the n-ch TFT should be set to be slightly higher than the boron concentration in the channel region of the p-ch TFT.
A method of manufacturing a conventional p-Si TFT substrate having an n-ch TFT of the partial GOLD structure (TFT for driving pixel), an n-ch TFT of the GOLD structure and a p-ch TFT (TFT for peripheral circuit) without LDD region will now be described with reference to FIGS. 32A to 41B. FIGS. 32A and 41B are sectional views of steps illustrating a conventional method of manufacturing the p-Si TFT. In FIGS. 32A to 41B, the region for forming the n-ch TFT (hereinafter also referred to as “first TFT”) of the GOLD structure is illustrated on the left side in the drawings, the region for forming the n-ch TFT (hereinafter also referred to as “second TFT”) of the partial GOLD structure is illustrated in the central portion of the drawings, and the region for forming the p-ch TFT (hereinafter also referred to as “third TFT”) is illustrated on the right side in the drawings.
Referring, first, to FIG. 32A, a silicon nitride film (SiN film) 112, a silicon oxide film (SiO2 film) 114 and an amorphous silicon (a-Si) film are formed on the whole surface of the glass substrate 110 in this order. Then, the whole surface of the a-Si film is channel-doped with boron (B ions) and, then, the a-Si film is laser-crystallized by using an excimer laser to form a p-Si film 120. Referring next to FIG. 32B, a resist is applied onto the whole surface of the substrate followed by patterning by using the first photomask to thereby form a resist pattern 101M. The resist pattern 101M is so formed as to cover the whole region for forming the third TFT. Then, by using the resist pattern 101M as a mask, the p-Si film 120 is additionally channel-doped with boron except the region for forming the third TFT. Then, the boron concentration in the channel region of the n-ch TFTs (first and second TFTs) becomes slightly higher than the boron concentration in the channel region of the p-ch TFT (third TFT).
Referring next to FIG. 33, a resist is applied to the whole surface of the substrate and is patterned by using a second photomask to form resist patterns 102M. The resist patterns 102M are so formed as to cover the whole regions for forming the first to third TFTs. Then, the p-Si film 120 is etched by using the resist patterns 102M as masks to form island-like p-Si films 120a, 120b and 120c. 
Referring next to FIG. 34, the resist is applied to the whole surface of the substrate and is patterned by using a third photomask to form resist patterns 103M. The resist patterns 103M are so formed as to cover a region that becomes the channel region of the first TFT, a region that becomes the channel region of the second TFT and the region for forming the third TFT. Then, by using the resist patterns 103M as masks, n-type impurities such as of phosphorus (P) are implanted at a low concentration. Then, n-type impurities are implanted into the p-Si film 121a on the region for forming the first TFT except the channel region 125a and into the p-Si film 121b in the region for forming the second TFT except the channel region 125b. 
Referring next to FIG. 35A, an insulating film (gate insulating film) 130 and a first electrically conducting thin film 132 that serves as a gate electrode are formed in this order on the whole surface of the substrate on the p-Si films 121a, 125a, 121b, 125b and 120c. Referring next to FIG. 35B, the resist is applied to the whole surface of the substrate and is patterned by using a fourth photomask to form resist patterns 104M. The resist patterns 104M are so formed as to cover the channel region 125a of the first TFT and the p-Si film 121a of the region that becomes the LDD region, the channel region 125b of the second TFT and the p-Si film 121b of the region (GOLD region) covered with the gate electrode of the LDD region, and the region that becomes the channel region of the third TFT. Then, by using the resist patterns 104M as masks, the electrically conducting thin film 132 is etched to form the gate electrodes 132a 132b and 132c. 
Referring next to FIG. 36, the resist is applied to the whole surface of the substrate and is patterned by using a fifth photomask to form resist patterns 105M. The resist patterns 105M are so formed as to cover the channel region 125b of the second TFT and the region that becomes the LDD region 123b, and the region where the third TFT is formed. Then, by using the resist patterns 105M and the gate electrode 132a as masks, n-type impurities such as of phosphorus are implanted at a high concentration. Then, there are formed a source region 122a and a drain region 124a of the first TFT, and a source region 122b and a drain region 124b of the second TFT.
Referring next to FIG. 37A, the resist is applied to the whole surface of the substrate and is patterned by using a sixth photomask to form resist patterns 106M. The resist patterns 106M are so formed as to cover the whole regions for forming the first and second TFTs. Then, by using the resist patterns 106M and the gate electrode 132c as masks, p-type impurities such as of boron are implanted at a high concentration. Then, a source region 122c and a drain region 124c are formed in the regions of the p-Si film 121c of the third TFT except the channel region 125c just under the gate electrode 132c. Next, the resist patterns 106M are peeled off, and the implanted impurities are activated by the irradiation with an excimer laser as illustrated in FIG. 37B.
Referring next to FIG. 38A, a first interlayer insulating film 134 is formed on the whole surface of the substrate on the gate electrodes 132a, 132b and 132c. Referring next to FIG. 38B, a resist is applied onto the whole surface of the substrate, and is patterned by using a seventh photomask to form resist patterns 107M. Then, by using the resist patterns 107M as masks, the interlayer insulating film 134 and the insulating film 130 are etched on the source regions 122a, 122b, 122c and on the drain regions 124a, 124b, 124c to form contact holes 136a, 136b and 136c. 
Referring next to FIG. 39A, a second electrically conducting thin film 138 that serves as source/drain electrodes is formed on the whole surface of the substrate on the first interlayer insulating film 134. Referring next to FIG. 39B, a resist is applied to the whole surface of the substrate and is patterned by using an eighth photomask to form resist patterns 108M. Then, by using the resist patterns 108M as masks, the electrically conducting thin film 138 is etched to form source electrodes 138a, 138b, 138c and drain electrodes 139a, 139b, 139c. Through the above steps, there are formed an n-ch TFT (first TFT) of the GOLD structure illustrated on the left side in FIG. 39B, an n-ch TFT (second TFT) of the partial GOLD structure illustrated in the central portion of FIG. 39B and a p-ch TFT (third TFT) without LDD region illustrated on the right side in FIG. 39B.
Referring next to FIG. 40, a second interlayer insulating film 140 is formed on the whole surface of the substrate on the source electrodes 138a, 138b and 138c, and on the drain electrodes 139a, 139b and 139c. Then, by using a ninth photomask, the interlayer insulating film 140 is removed by etching on the source electrode 138b of the second TFT which is for driving the pixel to form a contact hole 142b. 
Referring next to FIG. 41A, a third transparent electrically conducting film 144 that serves as pixel electrodes is formed on the whole substrate on the interlayer insulating film 140. Referring next to FIG. 41B, the electrically conducting film 144 is patterned by using a tenth photomask to form a pixel electrode 144b. Through the above steps, there is completed a p-Si TFT substrate including the n-ch TFT (TFT for driving the pixel) of the partial GOLD structure illustrated in the central portion of FIG. 41A, and n-ch TFT of the GOLD structure and p-ch TFT (TFT for peripheral circuit) without LDD region illustrated on the left side and on the right side in FIG. 41A.
When the n-ch TFTs of the GOLD structure and of the partial GOLD structure are formed as described above, it is not allowed to use the gate electrodes 132a and 132b as masks at the time of implanting n-type impurities at a low concentration into the p-Si films 121a and 121b except the channel regions 125a, 125b. Therefore, a step is newly required for forming the resist patterns 103M (see FIG. 34). Therefore, to form the CMOS circuits using the TFTs of the GOLD structure and of the partial GOLD structure, the step of photolithography is increased by at least one time as compared to when the TFTs of the non-GOLD structure are only used. To form the TFTs, therefore, eight or more times of photolithography steps are required. To manufacture the TFT substrate including the pixel electrode 144b, therefore, ten or more times of photo lithography steps are necessary resulting in a drop in the productivity of the TFT substrate and driving up the cost of manufacturing the TFT substrate.
Incidentally, the documents of the related art are as follows:
[Patent Document 1]
JP-A-2000-294787
[Patent Document 2]
JP-A-2001-13524